32Gbaud PAM4 Clock Recovery Module With A SFP28/56 Optical Port
U9720A CDR (Clock Recovery Module ) is mainly used to
provide clock recovery signal in the test environment without
triggering clock, so as to use the sampling oscilloscope to test
the optical eye diagram of the device. The typical application is
the testing of optical network equipment or the BOB prodUt in PON
application. Because the photometric device itself has no frequency
division clock output, it is necessary to recover the clock signal
to trigger the sampling oscilloscope when testing the optical eye
diagram.
U9720A CDR has a SFP28/56 optical port, which is suitable
for SFP28/56 encapsulated conventional SFP28/56, SR,LR,BIDI and
other optical modules. It is Support for NRZ and PAM4 signals. And
only needs the receiving end of the optical module to convert the
optical signal to the electrical signal, and then extract and
output the clock of the electrical signal. Clock signal is mainly
used for the trigger signal of oscilloscope.
32G clock recovery instrument is a kind of test
equipment for high speed digital communication system, which is
used to extract and recover the clock signal from the input signal.
In high-speed digital communications, the stability and accuracy of
the clock signal are crucial for the correct transmission of data.
Because the signal may be affected by noise, distortion and other
factors in the transmission process, resulting in the quality of
the clock signal decline, it is necessary to use the clock recovery
instrument to extract and recover high-quality clock signals.
Specification
| Technical index | Max | Min | Unit |
| Data rate range | 29 | 25 | Gbps/Gbaud |
| Wavelength range (single mode/multi-mode determined by module) | 1650 | 800 | nm |
| Optical input range (determined by module sensitivity) | +3 | -12 | dBm |
| Clock recovery output frequency division ratio | 2 / 4 / 8 / 16 / 64 / 256 |
|
| Output electrical clock amplitude | 500 (Typical value) | mVpp |
| CML clock differential output amplitude | 800 | 200 | mVpp |
| The clock output jitter randomly | 800 | 300 | fs |
| Clock frequency (28.1Gbps as an example) | 14.05 | 0.11 | GHz |
| Internal Signal Loss Detection (LOS) | 128 (overload) | 5 (Sensitivity) | mV |
| Power supply voltage (external power input voltage) | 5.5 | 4 | V |
| Operating temperature | 70 | 10 | ℃ |
| Adaptive module type (supports NRZ and PAM4 signals) | SFP28/56,SR,LR,BIDI |
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