CPLD 40K Programmable Logic Device Chip GW2A-LV18PG256C8/I7
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PBGA-256 CPLD/FPGA Programmable Logic Device Chip GW2A-LV18PG256C8/I7 When using the GW2A/GW2AR series FPGA products for circuit board design, users should follow a series of rules. This manual describes the features and special functions of the GW2A/GW2AR series FPGA products and provides a comprehensive checklist to guide the design process. The main contents of this guide are as follows: <s:1> Power supply <e:1> JTAG download <e:1> MSPI download <s:1> clock pin <e:1> differential pin <e:1> READY, RECONFIG_N DONE <s:1> mode <e:1> JTAGSEL_N <e:1> FASTRD_N <s:1> EXTR <e:1> pin multiplexing <s:1> external crystal oscillator circuit reference <s:1> GW2AR Bank voltage <e:1> supported configuration mode The youdaoplaceholder0 pin allocation Power supply 1. Overview The voltage types of the GW2A/GW2AR series FPGA products include Core voltage (VCC),PLL voltage (VCCPLL), auxiliary voltage (VCCX), and Bank Voltage (VCCIO). VCCX is an auxiliary power supply used to connect the internal parts of the chip and is usually powered by a 2.5V or 3.3V power supply. If VCCX does not exist,I/O,OSC and BSRAM circuits will be affected and the chip will not function properly. 2. Power index Users should ensure that GOWINSEMI products are always available www.gowinsemi.com 1 (14) Use within the range Schematic Manual of GW2A/GW2AR Series FPGA Products UG206-1.1 E Recommended working conditions and scope. The data exceeds the work. The conditions and scope are for reference only. GOWINSEMI does not guarantee that all equipment is in compliance with standards Operate as expected beyond the working conditions and scope. For specific densities, encapsulation and resource utilization, the GPA tool can Used for evaluating and analyzing power consumption. 4. Power-on time Reference range for power-on time :0.2 milliseconds to 2 milliseconds. Attention! Youdaoplaceholder7 If the power-on time exceeds 2 milliseconds, you need to make sure that in In the sequential power-on process, it starts with VCC, followed by VCCX/VCCIO. If the power-on time is less than 0.2 milliseconds, it is recommended to increase it Capacitors are used to extend the power-on time. 5. Power filter Each FPGA power input pin passes through a 0.1uF The ceramic capacitor is connected to ground. The input terminal of the VCC core voltage should mainly be carried out Noise processing. For specific reference, please refer to Figure 1: Figure 1 Noise processing at the core voltage input terminal of VCC V1P0 FB VCC C 4.7 uF GW2A/GW2AR series FPGA products isolation and filtering VCCPLL. For specific reference, please refer to Figure 2 www.gowinsemi.com 2 (14) Schematic Manual of GW2A/GW2AR Series FPGA Products UG206-1.1 E Figure 2 Isolation and Filtering of VCCPLL FB is a magnetic bead, reference model mh2029-221Y, with ceramic capacitors of 4.7uF,100nF and 10nF. It offers more than Accuracy of ±10%. Download JTAG 1. Overview JTAG download is used to download bitstream data to SRAM, FPGA with on-chip flash or off-chip flash. 2. Signal Definition Table 3 Signal Definitions of JTAG Configuration Mode Name I/O description Serial clock input in TCK I JTAG mode TMS I is weak internally Serial mode input in pull-up JTAG mode TDI I, weak internally Serial data input in pull-up JTAG mode Serial data output in TDO O JTAG mode 3. JTAG Circuit Reference Figure 3 Reference for the JTAG circuit Attention! The resistance accuracy shall not be less than 5%. The power supply at pin 6 of the youdaoplaceholder1 JTAG socket can be adjusted to VCC1P2. VCC1P5,VCC1P8 and VCC2P5, adjusted as needed.
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| Product Tags: CPLD Programmable Logic Device Chip 40K Programmable Logic Device Chip GW2A-LV18PG256C8/I7 |
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CPLD 40K Programmable Logic Device Chip GW2A-LV18PG256C8/I7 |
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