Siemens 6GK1143-0TB01 SIMATIC NET CP 1430 TF Communications Processor
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PRODUCT DETAILS
FP <Bit> (Positive RLO edge) detects a rising edge when the RLO transitions from"0"to"1"andindicates this by RLO= 1.During each program scan cycle, the signal state of the RLO bit is compared with that obtained inthe previous cycle to see if there
has been a state change. The previous RLO state must be stored in the edge flag address (<Bit>) to make the comparison. If there is
a difference between current and previous RLO"0"state (detection of rising edge), the RLO bit will be"1"after this instruction. Note:The instruction has no point if the bit you want to monitor is in the process image because the local data for a block are only valid
during the block's runtime.
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