Dual JK flip-flop with reset , negative - edge trigger 74HC107N,652

FEATURES

• Output capability: standard

• I_CC category: flip-flop

GENERAL DESCRIPTION

The 74HC/HCT107 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT107 are dual negative edge triggered

JK-type flip-flops featuring individual J, K, clock (nCP) and

reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable one set-up time prior to

the HIGH-to-LOW clock transition for predictable

operation.

The reset (nR) is an asynchronous active LOW input.

When LOW, it overrides the clock and data inputs, forcing

the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

QUICK REFERENCE DATA

GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns

Notes

1. C_PD is used to determine the dynamic power dissipation (P_D in µW):

         P_D = C_PD × V_CC² × fi + ∑ (C_L × V_CC² × f_o) where:

    f_i = input frequency in MHz

    f_o = output frequency in MHz

    ∑ (C_L × V_CC² × f_o) = sum of outputs

    C_L = output load capacitance in pF

    V_CC = supply voltage in V

2. For HC the condition is V_I = GND to V_CC

    For HCT the condition is V_I = GND to V_CC − 1.5 V.

PIN DESCRIPTION