Platform Flash In-System Programmable Configuration PROMs
Features
• In-System Programmable PROMs for Configuration of Xilinx® FPGAs
• Low-Power Advanced CMOS NOR Flash Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range (–40°C to +85°C)
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for
Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
• I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V
• Design Support Using the Xilinx ISE® Alliance and Foundation™
Software Packages
• XCF01S/XCF02S/XCF04S
♦ 3.3V Supply Voltage
♦ Serial FPGA Configuration Interface
♦ Available in Small-Footprint VO20 and VOG20 Packages
• XCF08P/XCF16P/XCF32P
♦ 1.8V Supply Voltage
♦ Serial or Parallel FPGA Configuration Interface
♦ Available in Small-Footprint VO48, VOG48, FS48, and FSG48
Packages
♦ Design Revision Technology Enables Storing and Accessing
Multiple Design Revisions for Configuration
♦ Built-In Data Decompressor Compatible with Xilinx Advanced
Compression Technology
Absolute Maximum Ratings
| Symbol |
Description | XCF01S, XCF02S,
XCF04S | XCF08P, XCF16P, XCF32P | Units |
| VCCINT | Internal supply voltage relative to GND | –0.5 to +4.0 | –0.5 to +2.7 | V |
| VCCO | I/O supply voltage relative to GND | –0.5 to +4.0 | –0.5 to +4.0 | V |
| VCCJ | JTAG I/O supply voltage relative to GND | –0.5 to +4.0 | –0.5 to +4.0 | V |
| VIN | Input voltage with respect to
GND | VCCO < 2.5V | –0.5 to +3.6 | –0.5 to +3.6 | V |
| VCCO ≥ 2.5V | –0.5 to +5.5 | –0.5 to +3.6 | V |
| VTS | Voltage applied to High-Z
output | VCCO < 2.5V | –0.5 to +3.6 | –0.5 to +3.6 | V |
| VCCO ≥ 2.5V | –0.5 to +5.5 | –0.5 to +3.6 | V |
| TSTG | Storage temperature (ambient) | –65 to +150 | –65 to +150 | °C |
| TJ | Junction temperature | +125 | +125 | °C |
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V
or 10 mA, whichever is easier to achieve. During transitions, the
device pins can undershoot to –2.0V or overshoot to +7.0V, provided
this overshoot or undershoot lasts less then 10 ns and with the
forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings
might cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time adversely affects device reliability.
3. For soldering guidelines, see the information on "Packaging and
Thermal Characteristics" at www.xilinx.com.
Supply Voltage Requirements for Power-On Reset and Power-Down
| Symbol |
Description | XCF01S, XCF02S,
XCF04S | XCF08P, XCF16P,
XCF32P | Units |
| Min | Max | Min | Max |
| TVCC | VCCINT rise time from 0V to nominal voltage(2) | 0.2 | 50 | 0.2 | 50 | ms |
| VCCPOR | POR threshold for the VCCINT supply | 1 | - | 0.5 | - | V |
| TOER | OE/RESET release delay following POR(3) | 0.5 | 3 | 0.5 | 30 | ms |
| VCCPD | Power-down threshold for VCCINT supply | - | 1 | - | 0.5 | V |
| TRST | Time required to trigger a device reset when the VCCINT supply drops below the maximum VCCPD threshold | 10 | - | 10 | - | ms |
Notes:
1. VCCINT, VCCO, and VCCJ supplies can be applied in any order.
2. At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating
voltage within the specified TVCC rise time. If the power supply cannot meet this requirement, then
the device might not perform power-on-reset properly.
3. If the VCCINT and VCCO supplies do not reach their respective recommended operating
conditions before the OE/RESET pin is released, then the
configuration data from the PROM is not available at the
recommended threshold levels. The configuration sequence must be
delayed until both VCCINT and VCCO have reached their recommended operating conditions.
