XC4VSX55-10FFG1148I electronic integrated circuit Platform Flash In-System Programmable Configuration PROMS

Virtex-4 Family Overview

General Description

The Virtex-4™ Family is the newest generation FPGA from Xilinx. The innovative Advanced Silicon Modular Block or ASMBL™ column-based architecture is unique in the programmable logic industry. Virtex-4 FPGAs contain three families (platforms): LX, FX, and SX. Choice and feature combinations are offered for all complex applications. A wide array of hard-IP core blocks complete the system solution. These cores include the PowerPC™ processors (with a new APU interface), Tri-Mode Ethernet MACs, 622 Mb/s to 11.1 Gb/s serial transceivers, voltage/temperature system monitor blocks, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 building blocks are an enhancement of those found in the popular Virtex-based product families: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, allowing upward compatibility of existing designs. Virtex-4 devices are produced on a state-of-the-art 90-nm copper process, using 300 mm (12 inch) wafer technology. Combining a wide variety of flexible features, the Virtex-4 family enhances programmable logic design capabilities and is a powerful alternative to ASIC technology.

SelectIO Technology

• Up to 960 user I/Os

• Wide selections of I/O standards from 1.5V to 3.3V

• Extremely high-performance

- 600 Mb/s HSTL & SSTL (on all single-ended I/O)

- 1 Gb/s LVDS (on all differential I/O pairs)

• True differential termination

• Selected low-capacitance I/Os for improved signal integrity

• Same edge capture at input and output I/Os

• Memory interface support for DDR and DDR-2 SDRAM, QDR-II, RLDRAM-II, and FCRAM-II

ChipSync Technology

• Integrated with SelectIO technology to simplify source-synchronous interfaces

• Per-bit deskew capability built in all I/O blocks (variable input delay line)

• Dedicated I/O and regional clocking resources (pin and trees)

• Built in data serializer/deserializer logic in all I/O and clock dividers

• Memory/Networking/Telecommunication interfaces up to 1 Gb/s+

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