MT48LC16M16A2P-75 IT:D Programmable Integrated Circuits Ics Chip 5A Current

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FEATURES

• PC66-, PC100-, and PC133-compliant

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst leCM GROUPhs: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes

• Self Refresh Mode

• 64ms, 8,192-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

OPTIONS MARKING

• Configurations 64 Meg x 4 (16 Meg x 4 x 4 banks)

64M4 32 Meg x 8 ( 8 Meg x 8 x 4 banks)

32M8 16 Meg x 16 ( 4 Meg x 16 x 4 banks) 16M16

• WRITE Recovery (t WR) t WR = “2 CLK”1 A2

• Package/Pinout 54-pin TSOP II OCPL2 (400 mil) TG 60-ball FBGA

(8mm x 16mm) (x4, x8) FB4, 5 54-ball FBGA (8mm x 14mm) (x16 only) FG

256 Mb SDRAM PART NUMBERS