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CDC3RL02YFPR Clock Timer ICS Clock Buffer 2Ch Square/Sine- to-Square Wave Clock

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CDC3RL02YFPR Clock Timer ICS Clock Buffer 2Ch Square/Sine- to-Square Wave Clock

Brand Name Ti
Model Number CDC3RL02YFPR
Minimum Order Quantity Contact us
Price Contact us
Payment Terms Paypal, Western Union, TT
Supply Ability 50000 Pieces per Day
Delivery Time The goods will be shipped within 3 days once received fund
Packaging Details DSBGA8
Description Clock Fanout Buffer (Distribution) IC 1:2 52 MHz 8-XFBGA, DSBGA
Supply Voltage - Max 5.5 V
Supply Voltage - Min 2.3 V
Minimum Operating Temperature - 40 C
Maximum Operating Temperature + 85 C
Max Output Freq 52 MHz
Operating Supply Current 50 mA
Detailed Product Description

CDC3RL02YFPR Clock Timer ICS Clock Buffer 2Ch Square/Sine- to-Square Wave Clock

 

1 Features

  • Low Additive Noise:
  • – –149 dBc/Hz at 10-kHz Offset Phase Noise

  • – 0.37 ps (RMS) Output Jitter

  • Limited Output Slew Rate for EMI Reduction (1- to 5-ns Rise/Fall Time for 10-pF to 50-pF Loads)

  • Adaptive Output Stage Controls Reflection

  • Regulated 1.8-V Externally Available I/O Supply

  • Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP (0.8 mm × 1.6 mm)

  •  

2 Applications

  • Cellular Phones

  • Global Positioning Systems (GPS)

  • Wireless LAN

  • FM Radio

  • WiMAX

  • W-BT

 

3 Description

The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. It buffers a single master clock, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output.

The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to- peak). CDC3RL02 has been designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines.

The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8-V supply is externally available to provide regulated power to peripheral devices such as a TCXO.

The CDC3RL02 is offered in a 0.4-mm pitch wafer- level chip-scale (WCSP) package (0.8 mm × 1.6 mm) and is optimized for very low standby current consumption.

Device Information

PART NUMBER

PACKAGE

BODY SIZE (NOM)

CDC3RL02

DSBGA (8)

0.80 mm × 1.60 mm

Product Tags: timer ic chip   time delay ic chip  
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