TMS320DM8168CCYG2 Mosfet Power Transistor DSP, DSC DaVinci Digital
Media Processor 1 Features 1 • High-Performance DaVinci Digital Media Processors – ARM® CortexTM-A8 RISC Processor • Up to 1.20 GHz – C674xTM VLIW DSP • ARM Cortex-A8 Core • Jazelle® RCT Execution Environment ARM Cortex-A8 Memory Architecture – 32-KB Instruction and Data
Caches – 256-KB L2 Cache – 64-KB RAM, 48-KB of Boot ROM TMS320C674x Floating-Point VLIW DSP – 64 General-Purpose Registers (32-Bit) – Six ALU (32-Bit and 40-Bit) Functional Units Supports 32-Bit Integer, SP (IEEE Single Precision, 32-Bit) and DP
(IEEE Double Precision, 64-Bit) Floating Point Supports up to Four SP Adds Per Clock and Four DP Adds Every Two
Clocks Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal
or Square Root Operations Per Cycle
– Two Multiply Functional Units Mixed-Precision IEEE Floating-Point Multiply Supported up to: – 2SPxSP→SPPerClock – 2SPxSP→DPEveryTwoClocks – 2SPxDP→DPEveryThreeClocks –
2DPxDP→DPEveryFourClocks Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x
16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8- Bit
Multiplies per Clock Cycle
C674x Two-Level Memory Architecture – 32-KB L1P and L1D RAM and Cache – 256-KB L2 Unified Mapped RAM and Caches
• System Memory Management Unit (System MMU) – Maps C674x DSP and
EMDA TCB Memory Accesses to System Addresses • 512KB of On-Chip Memory Controller (OCMC) RAM • Media Controller – Manages HDVPSS and HDVICP2 Modules • Up to Three Programmable High-Definition Video Image Coprocessing (HDVICP2) Engines – Encode, Decode, Transcode Operations – H.264, MPEG-2, VC-1, MPEG-4 SP and ASP • SGX530 3D Graphics Engine (Available Only on the DM8168 Device) – Delivers up to 30 MTriangles per Second – Universal Scalable Shader Engine – Direct3D® Mobile, OpenGL® ES 1.1 and 2.0, OpenVGTM 1.1, OpenMaxTM
API Support – Advanced Geometry DMA Driven Operation – Programmable HQ Image Anti-Aliasing • Endianness – ARM, DSP Instructions and Data – Little Endian • HD Video
Processing Subsystem (HDVPSS) – Two 165-MHz HD Video Capture Channels One 16-Bit or 24-Bit and One 16-Bit Channel Each Channel Splittable Into Dual 8-Bit Capture Channels – Two 165-MHz HD Video Display Channels • One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel – Simultaneous SD and HD Analog Output – Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock – Three Graphics Layers • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
– Supports up to DDR2-800 and DDR3-1600 – Up to Eight x8 Devices Total – 2GB of Total Address Space – Dynamic Memory Manager (DMM) Programmable Multi-Zone Memory Mapping and Interleaving Enables Efficient 2D Block Accesses Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring Optimizes Interlaced Accesses • One PCI Express® (PCIe) 2.0 Port with Integrated PHY
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