XC3S1600E-4FGG320I FPGA chip Enhanced Double Data Rate Support Nanometer Process

XC3S1600E-4FGG320I Features

• Very low cost, high-performance logic solution for high-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 376 I/O pins or 156 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• 622+ Mb/s data transfer rate per I/O

• True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O
• Enhanced Double Data Rate (DDR) support
• DDR SDRAM support up to 333 Mb/s
• Abundant, flexible logic resources

• Densities up to 33,192 logic cells, including optional shift register or distributed RAM support
• Efficient wide multiplexers, wide logic
• Fast look-ahead carry logic
• Enhanced 18 x 18 multipliers with optional pipeline
• IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
• Up to 648 Kbits of fast block RAM

• Up to 231 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 300 MHz)