8Gb C Die DRAM Memory Chip DDR4 SDRAM K4A8G165WC-BITD

Dynamic Random Access Memory DRAM 8Gb C-die DDR4 SDRAM K4A8G165WC-BITD

JEDEC standard 1.2V(1.14V-1.26V)
VDDo = 1.2V(1.14V-1.26V)
VPp=2.5V(2.375V-2.75V)
800 MHz fek for 1600Mb/sec/pin, 933 MHz fek for 1866Mb/sec/pin,1067MHz fck for 2133Mbsec/pin, 1200MHz fck for 2400Mbsec/pin1333MHz fck for 2666Mbsec/pin, 1600MHz fck for 3200Mb/sec/pin
8 Banks (2 Bank Groups)
Programmable CAS Latency (posted CAS):
10.11.12,13.14.15,16,17.18.19.20.22.24
Programmable CAS Write Latency(CWL)=9,11 (DDR4-1600), 10,12(DDR4-1866),11,14 (DDR4-2133),12,16(DDR4-2400),14.18 (DDR4.2666)and 16.20(DDR4-3200)
8-bit pre-fetch
Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read orwrite [either On the fiy using A12 or MRS]
Bi-directional Differential Data-Strobe
Internal (self) calibration: Internal self calibration through ZQ pin
(RZQ: 240 ohm±1%)
The 8Gb DDR4 SDRAM C-die is organized as a 64Mbit x 16 l/Os x 8banksdevice. This synchronous device achieves high speed double-data-ratetransfer rates of up to 3200Mbsecpin (DDR4-3200) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration,On Die Termination using ODT pin and Asynchronous Reset.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of dif.ferential clocks (CK rising and CK falling). All l/Os are synchronized with apair of bidirectional strobes (DQS and DQS) in a source synchronous fash.ion. The address bus is used to convey row, column, and bank addressinformation in a RAS/CAS multiplexing style. The DDR4 device operateswith a single 1.2V(1.14V-1.26V)power supply, 1.2V(1.14V~1.26V) VDDOand 2.5V(2.375V-2.75V)VPP.
The 8Gb DDR4 C-die device is available in 96ball FBGAs(x16)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower than TcAsE 85°C, 3.9us at 85°C <
TCASE ≤ 95 °C
Support industrial Temp (-40 ~ 95°C)-tREFI7.8us at -40°C≧TCASE ≤85°C-tREFI3.9us at 85“C<TCASE ≤ 95°CConnectivity Test Mode iTEN) is Supported
Asynchronous Reset
Package: 96 balls FBGA-x16
All of Lead-Free products are compliant for RoHS
All of products are Halogen-free
CRC (Cyclic Redundancy Check) for Read'Write data security
Command address parity check
DBl (Data Bus Inversion)
Gear down mode
POD (Pseudo Open Drain) interface for data inputoutput
Internal VREF for data inputs
External PP for DRAM Activating Power
PPR and sPPR is supported

Packaging and transportation instructions

- According to the standard export packaging.

Customers can choose from cartons, wooden cases and wooden pallets according to their own requirements.

Q&A

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This depends on the quantity of the order and the season in which you place the order. Usually, we can ship the goods within 7 to 15 days (for small batches), and for large batches, it takes about 30 days.

3. What are your payment terms?

Factory price, 30% deposit, 70%T/T payment before shipment.

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It can be transported by sea, air or express delivery (EMS, UPS, DHL, TNT, FEDEX, etc.). Please confirm with us before placing an order.

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